BART-based prediction of cache reliable energy-efficiency

Abstract

Performance, energy consumption and soft error have become parallel important design concerns for microprocessors. As the largest on-chip structures, cache memories play an impressive role in microprocessor design. The awareness of cache reliable energy-efficiency is highly important for microprocessor designers, especially at early design stage. The dynamic behavior of cache reliable energy-efficiency has been characterized, motivating the development of predicting reliable energy-efficiency to track runtime characteristics of cache. In this paper, a BART (Bayesian Additive Regression Trees) model is created to predict the reliable energy-efficiency of Level-1 data cache (L1D) accurately across different execution phases and benchmarks, as well as to illustrate the effects of performance metrics on L1D reliable energy-efficiency. Experimental results demonstrate the accuracy of BART in reliable energy-efficiency prediction, and present the intrinsic correlation between reliable energy-efficiency and the key performance metrics.