Transistor sizing and folding techniques for radiation hardening

Abstract

The efficiency of transistor sizing and folding techniques to mitigate SET in CMOS circuits is evaluated using circuit and device simulations. According to the LET of the ionizing particle, the SET can be more or less filtered by these methods. Based on the results of the circuit and device simulations, a novel technique able to reduce the SET effect is proposed. The method combines transistor sizing, folding and resistors. The technique was applied in a chain of inverters and SRAM cell.