Design and characterization of Hall Plates in a 0.5μm CMOS process

Abstract

Four different N-well Hall Plate geometries were designed and fabricated in a 0.5μm CMOS process provided by MOSIS. Different shapes, sizes, contact distribution and dimensions were used in order to characterize Hall Plate sensitivity and resistance in a range of temperatures from -40°C up to 165°C. To remove the offset a four-phase current spinning method was used. The results show a better sensitivity performance in the cross-shaped whereas the small square shape has a slight improvement in the SNR behavior. The sensitivity of the different Hall Plate geometries was simulated using a model based on finite-element showing good agreement with the measurements.