CA based implementation of March test for high speed memories

Abstract

This work proposes an efficient realization of March test for fault detection in high speed memories. The realization is based on the theory of a modeling tool called cellular automata (CA). A special class of CA architecture referred to as the SACA is considered for the test logic design. The test logic/hardware thus developed operates on the data read from the memory during March. It outputs an one-bit signature to detect faults in the memory chip, effectively reducing the comparison time required in conventional realization. The regular structure of CA enables low cost implementation of the test hardware for a memory chip, that is inherently regular in structure. The introduction of segmented CA structure further enables the drastic reduction in testing time.