Lithography simulator for EB/DUV intra-level mix and match

Abstract

EB/DUV intra-level mix and match (ILM&M) will make possible realization of both patterning finer than is attainable with DUV lithography and throughput higher than in the case of exposure only by EB writer. In order to realize the EB/DUV-ILM&M, the following two problems must be overcome. (1) The final size of the DUV exposed pattern is changed due to the influence of the position of EB exposed pattern, because of exposure to widely distributed back-scattered electrons. (2) Patterns exposed respectively by EB and DUV are separated or overlapped, due to moving of wafers in and out of each exposure apparatus, and their different registration methods. These problems make it very difficult to fabricate electronic devices that operate satisfactorily. Therefore, simulation of the ILM&M process is a prerequisite for fruitful examination of fabrication in the presence of these problems. We developed a lithography simulator corresponding to the EB/DUV-ILM&M process.