Next generation IP Router architecture using SFQ technology

Abstract

An innovative IP router architecture from the viewpoint of minimum switching delay, switching capacity, QoS assurance for the next generation Internet services is proposed. We examined the IP router performance using superconductor device simulator. For the evaluation of a novel IP switch architecture, we effectively apply the SFQ circuits using Josephson junctions to an extremely restricted function block in the switching node and a conventional semiconductor technology is also applied for the rest parts of the other function blocks inside it. We designed frame compression circuits and investigated their behavior by computer simulation using "WinS". We assumed the NEC's standard fabrication process of Nb junction LSI. The simulation results show that the bias current margin of the input shift register, and control circuit is plusmn55%, and plusmn33%, respectively. We also confirmed in the simulation that these circuits could be properly operated up to the clock frequency of 22 GHz