Reconfigurable signal processor for channel coding and decoding in low SNR wireless communications

Abstract

An area and computational-time efficient turbo decoder implementation on a reconfigurable processor is presented. The turbo decoder takes advantage of the latest sliding window algorithms to produce a design with minimal storage requirements as well as offering the ability to configure key system parameters via software. The parameter programmability allows the decoder to be used in a research environment to study less understood aspects of turbo codes.