{"title":"High-accuracy programmable timing generator with wide-range tuning capability","authors":"Ting-Li Chu, Sin-Hong Yu, Chorng-Sii Hwang","doi":"10.1109/ISPACS.2012.6473504","DOIUrl":null,"url":null,"abstract":"In this paper, a high-accuracy programmable timing generator with wide-range tuning capability is proposed. With the aid of dual delay-locked loop (DLL), both of the coarse and fine tuning mechanisms are operated in precise closed-loop scheme to lessen the effects of the ambient variations. The timing generator can provide sub-gate resolution and instantaneous switching capability. The circuit is implemented and simulated in TSMC 0.18 μm 1P6M technology. The test chip area occupies 1.9 mm2. The reference clock cycle can be divided into 128 bins by interpolation to obtain 14 ps resolution with the clock rate at 550 MHz. The INL and DNL are within -0.21~+0.78 and -0.27~+0.43 LSB, respectively.","PeriodicalId":158744,"journal":{"name":"2012 International Symposium on Intelligent Signal Processing and Communications Systems","volume":"79 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Symposium on Intelligent Signal Processing and Communications Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPACS.2012.6473504","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, a high-accuracy programmable timing generator with wide-range tuning capability is proposed. With the aid of dual delay-locked loop (DLL), both of the coarse and fine tuning mechanisms are operated in precise closed-loop scheme to lessen the effects of the ambient variations. The timing generator can provide sub-gate resolution and instantaneous switching capability. The circuit is implemented and simulated in TSMC 0.18 μm 1P6M technology. The test chip area occupies 1.9 mm2. The reference clock cycle can be divided into 128 bins by interpolation to obtain 14 ps resolution with the clock rate at 550 MHz. The INL and DNL are within -0.21~+0.78 and -0.27~+0.43 LSB, respectively.