Low-cost DC BIST for analog circuits: A case study

Abstract

This paper presents a DC analog testing technique based on a simple voltage comparison of the highest sensitivity-to-faults node, which is found by simulation. The technique is a structural, fault driven testing approach and can be applied to any analog circuit with very few extra added circuitry. A proof of concept has been implemented in a 65nm low-voltage transconductor, showing good fault coverage for both catastrophic and parametric faults.