System clock reduction based on multiple sampling for digital switching power supplies

Abstract

In this paper, the proposed sampling structure based on one-comparator sampling is presented, which can significantly reduce the system clock frequency from 100MHz to 25MHz, so as to reduce chip area. This method is verified by a synchronously-rectified buck converter with a switching frequency of 200kHz, and the digital controller takes as a control kernel the EP1C3T100 FPGA created by Altera Co., along with the VHDL language to program this controller.