Ultra-low-power CMOS technologies

Abstract

The fast growing portable-electronics market as well as thermal dissipation, reliability, and scalability issues have launched a massive trend towards low-power and low-voltage technologies. This has lead to a new, reduced standard digital CMOS supply voltage of 3.3 V reducing the power consumption by 70%. However, the power consumption can still be cut down substantially by reducing the supply and threshold voltages much further without compromising systems performance. A loss in device speed can be compensated on the systems level by appropriate parallel architectures. Based on this concept of ultra-low-power CMOS technologies we explore the lower limits of CMOS supply voltage and switching energy for a variety of circuit classes analytically and numerically. Ultra-low-power (ULP) process and device design, device modeling, performance evaluation, and the specific problems associated with ULP mixed-analog-digital technologies are discussed.