IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency

Abstract

On-chip interconnect structures become much more complicated and dominate system performance in multi-core SoCs. Oscillation ring test is an efficient test method for most types of faults in the interconnect structures, and previous studies show that a 100% fault coverage and good diagnosis resolution for various fault models is achievable. The test time of oscillation ring test is decided by the number of test sessions required to form all the rings. Previous method on ring generation algorithm uses depth-first-search (DFS) based method to generate long rings that may pass more uncovered edges. However, very few of the long rings can be put into the same test session, and thus the number of test sessions is not necessarily smaller. In this paper, we present several techniques to generate rings that can be tested concurrently. (1) Two ring generation algorithms are proposed to generate shorter rings that can be applied in parallel to reduce overall test time. (2) Multilevel framework is applied to optimize parallelism. Experimental results show that the proposed ring generation algorithms improve test application time by 2.25X, and with multilevel framework the improvement is 4.13X. All the ring generation algorithms achieve 100% interconnect fault coverage.