An analytical gate tunneling current model of Re-S/D SOI MOSFETs

Abstract

This paper presents an analytical direct gate tunneling current model of recessed-source/drain(Re-S/D) SOI MOSFET. The gate tunneling current behavior has been analyzed by varying different parameters like gate insulator thickness and drain to source voltage. The gate tunneling current has been investigated with the effect of high-k dielectric constant. 2D ATLAS tool has been used to validate the model results.