3D simulation study of 375V partial SOI SJ LDNMOS BDS limitation

Abstract

This paper investigates novel techniques of extending the breakdown voltage (BDS) capability of the partial silicon-on-insulator SJ LDNMOS up to 460V. This is based on a unique combination of two different concepts and technologies, namely the Partial Silicon-On-Insulator (PSOI) and Superjunction (SJ) to achieve a highly effective platform for Power Integrated Circuit. The device BDS sensitivity to the handle wafer diode voltage is mitigated by using a novel 3D design based on “domain decomposition” 3D TCAD simulations. The hot spot location in the complex termination area, which is due to out-of-plane (90°) bending of electrostatic potential lines towards the midpoint of the device area, is successfully identified and eliminated.