Real-time digital predistortion for radio frequency power amplifier linearization

S. Ferguson, A. Chopra
{"title":"Real-time digital predistortion for radio frequency power amplifier linearization","authors":"S. Ferguson, A. Chopra","doi":"10.1109/IEEE-IWS.2016.7585463","DOIUrl":null,"url":null,"abstract":"In this paper, a system is proposed for real-time calculation of digital predistortion (DPD) coefficients to linearize wideband radio frequency (RF) power amplifiers (PAs). The proposed system leverages the commercially available National Instruments (NI) PXIe-5646R vector signal transceiver (VST) platform. The VST is a single module RF instrument that combines a 200MHz instantaneous vector signal analyzer (VSA) and vector signal generator (VSG) with a shared Xilinx LX240T field-programmable gate array (FPGA). The FPGA is used to perform look-up table (LUT) predistorter estimation and predistortion in real-time. The proposed system is shown to reduce the time to generate a predistorted waveform by over two orders of magnitude compared to a software implementation. Furthermore, the linearity achieved with the proposed FPGA implementation closely matches a traditional software-based approach, with 15dB improvement in adjacent channel leakage ratio (ACLR) and a 3x improvement in error vector magnitude (EVM) for a 3G mobile handset power amplifier.","PeriodicalId":185971,"journal":{"name":"2016 IEEE MTT-S International Wireless Symposium (IWS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE MTT-S International Wireless Symposium (IWS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEEE-IWS.2016.7585463","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

In this paper, a system is proposed for real-time calculation of digital predistortion (DPD) coefficients to linearize wideband radio frequency (RF) power amplifiers (PAs). The proposed system leverages the commercially available National Instruments (NI) PXIe-5646R vector signal transceiver (VST) platform. The VST is a single module RF instrument that combines a 200MHz instantaneous vector signal analyzer (VSA) and vector signal generator (VSG) with a shared Xilinx LX240T field-programmable gate array (FPGA). The FPGA is used to perform look-up table (LUT) predistorter estimation and predistortion in real-time. The proposed system is shown to reduce the time to generate a predistorted waveform by over two orders of magnitude compared to a software implementation. Furthermore, the linearity achieved with the proposed FPGA implementation closely matches a traditional software-based approach, with 15dB improvement in adjacent channel leakage ratio (ACLR) and a 3x improvement in error vector magnitude (EVM) for a 3G mobile handset power amplifier.
射频功率放大器线性化的实时数字预失真
本文提出了一种实时计算数字预失真(DPD)系数的系统,用于线性化宽带射频功率放大器(pa)。该系统采用美国国家仪器公司(NI)的PXIe-5646R矢量信号收发器(VST)平台。VST是一种单模块射频仪器,结合了200MHz瞬时矢量信号分析仪(VSA)和矢量信号发生器(VSG)以及共享的Xilinx LX240T现场可编程门阵列(FPGA)。该FPGA用于实时执行查找表预失真估计和预失真。与软件实现相比,所提出的系统可以将产生预失真波形的时间减少两个数量级以上。此外,所提出的FPGA实现实现的线性度与传统的基于软件的方法非常接近,相邻通道泄漏比(ACLR)提高了15dB,误差矢量幅度(EVM)提高了3倍,用于3G手机功率放大器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信