A 130 nm CMOS PLL for Phase-II ATLAS-MDT TDC

Abstract

Global Project: Development of a TDC for ATLAS MDT Phase-II Upgrade Features: • Trigger-less and trigger mode • Edge and pair modes • Programmable output lines rates: 80 (legacy), 320, 640 Mbps • Re-design in TSMC 130nm technology – Clock and phase generator (ePLL) • 4 clock phase time interpolator @320MHz  3,125 ns/4 = 0,78ns LSB – TDC time-digitization unit (x24) and digital processing logics Trigger and readout scheme for the Phase-II MDT system