Q20D080 analog RAM logic array

C. Blake, M. Hollabaugh
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Abstract

An ECL (emitter-coupled logic)-structured array containing 1520 logic cells, 2560 bits of RAM, and a customizable analog section is described. The special needs of high performance VLSI testers was the driving force behind its organization and architecture. The chip is fabricated with a trench isolation bipolar process with 1-μm features, double layers of polysilicon, and triple layers of metallization
Q20D080模拟RAM逻辑阵列
描述了一个ECL(发射器耦合逻辑)结构阵列,其中包含1520个逻辑单元,2560位RAM和可定制的模拟部分。高性能VLSI测试仪的特殊需求是其组织和架构背后的驱动力。该芯片采用沟槽隔离双极工艺,具有1-μm的特征,双层多晶硅和三层金属化
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