Computer Simulation Results for a W-CDMA Frequency Synthesizer

Abstract

This paper describes the design and simulation of a frequency synthesizer in a standard 0.18 um CMOS technology. The performance of the charge pump is very important in determining the quality of frequency synthesizers. In designing the charge pump, we need to consider various issues such as current mismatch, charge sharing, feed through, and charge injection. This paper focuses on the current mismatch. An LC VCO was used for good phase noise characteristics. It is composed of np-core for negative resistance and p- tail for current source. An accumulation mode MOS varactor is used for frequency tuning, which has wide tuning range. A divider which scales from 423 to 434 is implemented by pulse swallow method. The entire design is verified through extensive computer simulation.