Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs

Abstract

State-of-art SRAM designs use either the negative bit line or the overdrive word line write assist circuits to improve the write-ability in a low voltage VDDMIN environment. But at the higher voltage operations, these write assist circuits will have an adverse effect on the SRAM bit cell's pass gate oxide tox reliability like hot carrier injection and time-dependent dielectric breakdown (TDDB). In this paper, we propose a novel two phase write scheme to improve the write-ability in a VDDMIN environment. We achieved improved write-ability by driving the word line voltage level to the power supply rail, in conjunction with the medium-sized SRAM bit cell. Simulation results at VDDMIN voltage of 0.52V in 16nm TSMC FinFET technology, demonstrate that the worst 5σ bit cell write margin is improved by 85mV. Our two phase write scheme with the word line voltage level restricted to the power supply rail, does not risk the bit cell's pass gate tox reliability at the higher voltage operations. We also present the two phase write scheme macro implementation for a column multiplexed SRAM architecture.