The role of test structures for yield enhancement and yield ramp-up: an example of adoptive yield enhancement (AYE): n/sup +//p-well junction leakage enhanced the abnormal leakage current of NMOS's parasitic NPN-BJT

Abstract

The yield loss of an 0.25 /spl mu/m SRAM caused by the n/sup +//p-well junction leakage was characterized and categorized in two areas by physical location: one is located at the gate/drain region, the other is at the corner of shallow trench isolation. For timely and efficient solving and monitoring of the fabrication line, two sets of test structures and corresponding measurement methods were designed for process monitoring and yield screening. Finally, based on the yield learning, we propose a test-structure-based process control and yield monitoring, called Adoptive Yield Enhancement (AYE).