A fast adder design using signed-digit numbers and ternary logic

T. N. Rajashekhara, I. Chen
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引用次数: 17

Abstract

The advantage of carry free addition offered by signed-digit numbers is exploited in designing a fast adder circuit. Signed-digit numbers with radix 2 and digit set (-1,0,1), called redundant binary signed-digit (RBSD) numbers, are used in the design. Ternary logic circuits using an MOS/CMOS combination are employed. The ternary logic and RBSD number system complement each other well because one ternary bit can support one RBSD digit. This provides an advantage over using binary logic where more than one bit would be needed to support one RBSD digit. While the RBSD number system offers faster add times because of carry free addition, ternary logic offers reduced circuit complexity in terms of both transistor count and interconnections. All circuit implementations were simulated and verified for satisfactory performance using SPICE software on a SUN workstation.<>
一个使用符号数字和三元逻辑的快速加法器设计
利用符号数免进位加法的优点,设计了一种快速加法器电路。设计中使用基数为2和数字集(-1,0,1)的有符号数字,称为冗余二进制有符号数字(RBSD)数。采用MOS/CMOS组合的三元逻辑电路。三进制逻辑与RBSD数字系统相辅相成,因为一个三进制位可以支持一个RBSD数字。与使用二进制逻辑相比,这提供了一个优势,因为二进制逻辑需要多个比特来支持一个RBSD数字。由于无进位加法,RBSD数字系统提供了更快的加法时间,而三元逻辑在晶体管数量和互连方面都降低了电路的复杂性。在SUN工作站上,用SPICE软件对所有电路实现进行了仿真,并验证了令人满意的性能。
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