{"title":"Ultra high aspect-ratio and thick deep silicon etching (UDRIE)","authors":"Y. Tang, A. Sandoughsaz, K. Najafi","doi":"10.1109/MEMSYS.2017.7863504","DOIUrl":null,"url":null,"abstract":"We report an advanced deep-reactive-ion-etching (DRIE) process developed specifically for etching ultra-deep structures in thick (>500μΉ) silicon wafers with high aspect-ratio and straight sidewalls across a wide range of feature sizes and patterns. This is achieved by ramping critical process parameters throughout the etching duration. 600–800μm deep trenches with widths as small as 20–40μm are etched in 1mm-thick silicon wafer, and are expected to be etched through a 1mm wafer with thicker and/or higher selectivity masking materials. We have produced holes >500μm deep with hole diameters as small as 25μm, and potentially with 10–15μm diameter holes. This ultra-deep silicon etching process will benefit both IC integration and emerging MEMS applications at micrometer and millimeter scale that demand high-resolution deep DRIE.","PeriodicalId":257460,"journal":{"name":"2017 IEEE 30th International Conference on Micro Electro Mechanical Systems (MEMS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 30th International Conference on Micro Electro Mechanical Systems (MEMS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MEMSYS.2017.7863504","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
Abstract
We report an advanced deep-reactive-ion-etching (DRIE) process developed specifically for etching ultra-deep structures in thick (>500μΉ) silicon wafers with high aspect-ratio and straight sidewalls across a wide range of feature sizes and patterns. This is achieved by ramping critical process parameters throughout the etching duration. 600–800μm deep trenches with widths as small as 20–40μm are etched in 1mm-thick silicon wafer, and are expected to be etched through a 1mm wafer with thicker and/or higher selectivity masking materials. We have produced holes >500μm deep with hole diameters as small as 25μm, and potentially with 10–15μm diameter holes. This ultra-deep silicon etching process will benefit both IC integration and emerging MEMS applications at micrometer and millimeter scale that demand high-resolution deep DRIE.