Fault characterisation of complementary pass-transistor logic circuits

Abstract

Complementary pass-transistor logic (CPL) circuits result in speed improvement and power reduction compared to conventional static CMOS logic. However, the behaviour of this logic family under fault has not yet been studied. This paper presents the results of an investigation into the behaviour of CPL circuits under various single faults. It is shown that all single transistor stuck-on faults are only detectable by I/sub DDQ/ testing, while all single stuck-open faults are only detectable by logic monitoring. The majority of the single bridging faults between the gate and source/drain terminals of the MOS transistors can be detected by current monitoring while a few are undetectable.