{"title":"Compute Express Link®: An open industry-standard interconnect enabling heterogeneous data-centric computing","authors":"Debendra Das Sharma","doi":"10.1109/HOTI55740.2022.00017","DOIUrl":null,"url":null,"abstract":"Compute Express Link is an open industry standard interconnect offering caching and memory semantics on top of PCI Express®. In addition to providing high-bandwidth and low-latency connectivity between host processor and accelerators, smart network interface card, and memory expansion devices, it also enables resource pooling across multiple systems for scalable, power-efficient and cost-effective computing. This paper delves into the micro-architectural design to deliver power-efficient performance based on our experience designing a Xeon CPU and FPGA with this technology with demonstrated silicon interoperability.","PeriodicalId":115402,"journal":{"name":"2022 IEEE Symposium on High-Performance Interconnects (HOTI)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on High-Performance Interconnects (HOTI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTI55740.2022.00017","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
Abstract
Compute Express Link is an open industry standard interconnect offering caching and memory semantics on top of PCI Express®. In addition to providing high-bandwidth and low-latency connectivity between host processor and accelerators, smart network interface card, and memory expansion devices, it also enables resource pooling across multiple systems for scalable, power-efficient and cost-effective computing. This paper delves into the micro-architectural design to deliver power-efficient performance based on our experience designing a Xeon CPU and FPGA with this technology with demonstrated silicon interoperability.