Enabling Power-Efficient Designs with III-V Tunnel FETs

2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2014-10-01 DOI:10.1109/CSICS.2014.6978551

M. Kim, Huichu Liu, Karthik Swaminathan, Xueqing Li, S. Datta, V. Narayanan

引用次数: 13

Abstract

III-V Tunnel FETs (TFET) possess unique characteristics such as steep slope switching, high gm/IDS, uni-directional conduction, and low voltage operating capability. These characteristics have the potential to result in energy savings in both digital and analog applications. In this paper, we provide an overview of the power efficient properties of III-V TFETs and designs at the device, circuit and architectural level.

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利用III-V隧道场效应管实现节能设计

III-V型隧道场效应管(TFET)具有陡坡开关、高gm/IDS、单向导通和低电压工作能力等特点。这些特性有可能在数字和模拟应用中节省能源。在本文中，我们概述了III-V tfet的功率效率特性以及器件，电路和架构级别的设计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

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