A Low Jitter Low Power and Wide Tuning Range Differential Ring Oscillator Topology in 28nm CMOS Technology for Clock Synthesizer Applications

Abstract

The Differential Ring Oscillator (DRO)-based VCO design involves many tradeoffs between frequency generation, phase noise, tuning range, power and area. Generally a lower phase noise design requires an higher current consumption, or a wider tuning range can be achieved at expense of higher noise level. In this paper, a 0.9-V differential ring oscillator (DRO) implemented in a 28nm CMOS technology is presented. Using very simple current-controlled delay cells, the proposed VCO achieves a wide operating frequency range from 1.10 to 1.62 GHz with a relatively constant output amplitude and excellent linearity between the output frequency and the input control current. Both theory and simulation show that the root-mean-square (rms) timing jitter is as small as 0.5 ps. The phase noise is −143.8 dBc/Hz at 10 MHz offset from the carrier frequency. The power supply sensitivity is 5.5%/V, the temperature coefficient is +500 ppm/degC, and the power consumption is 3 mW at nominal conditions. The area occupation is relatively smaller due to the simplicity and the low number of the delay cell used.