Design of a High-Performance DC Power Cycling Test Setup for SiC MOSFETs

Abstract

In this paper, a high-performance DC power cycling setup dedicated for SiC power MOSFETs is presented. Different from the previous DC power cycling setup designs focusing on circuit topology and operation principle, this paper discusses the detailed design considerations to ensure the measurement accuracy and control the voltage spikes within the safe voltage range of the data acquisition (DAQ) equipment. Specifically, the transient behavior of the circuit is analyzed, and a simulation model is built in LTspice to facilitate the design. From the simulation result, it is observed that the gate timing control is critical to limit the measurement spikes. In addition, adding decoupling capacitors helps to attenuate the ringing noise in the voltage measurement. A prototype is built, and the experimental results indicate that a precise measurement can be realized with the proposed DC power cycling setup under various conditions.