Analysis of DC Self Heating Effect in Stacked Nanosheet Gate-All-Around Transistor

Abstract

In this paper, self-heating effect in newly introduced stacked nanosheet gate-all-around transistor is investigated and discussed, and several architecture parameters such as metal gate thickness, number of channels, thermal conductivity of ILD and channel thickness affecting thermal reliability of nanosheet FET are studied through simulations. It is illustrated that nanosheet FET shows great lattice temperature variations and thermal resistance fluctuations from changes in such architecture parameters, and these can be mitigated by increasing thermal conductivity of ILD, and metal gate thickness.