Study of the piezoresistive properties of NMOS and PMOS Ω-gate SOI nanowire transistors: Scalability effects and high stress level

Abstract

We hereby present a comprehensive study of piezoresistive properties of aggressively scaled MOSFET devices. For the first time, the evolution of the piezoresistive coefficients with scaled dimensions is presented (gate length down to 20nm and channel width down to 8nm), and from the low to high stress regime (above 1GPa). We have shown that the downscaling of geometrical parameters doesn't allow the use of the conventional definition of piezoresistivity tensor elements. The obtained results give a comprehensive insight on strain engineering ability in aggressively scaled CMOS technology.