Suppression on Crosstalk Voltages of Paralleled SiC MOSFETs with Optimized Gate Configurations and Additional SiC SBDs

Abstract

It is popular to parallel SiC MOSFETs for high-current applications. Compared with the single SiC MOSFET chip, the cross-turn-ON issues of paralleled SiC MOSFETs (PSMs) will be more complicated because of various mismatches in PSMs. This paper investigates the effects of all possible mismatches on the spurious gate-source voltages of PSMs (crosstalk voltages) by theoretical analysis and experiments. It is found that mismatched body diodes, asymmetric power-net layout and uneven junction temperature for PSMs can increase crosstalk voltages, leading to higher cross-turn-ON risk. Then the proportion of overall and separate gate resistance is adjusted and additional SiC Schottky Barrier diodes (SBDs) are employed to suppress crosstalk voltages of PSMs due to these mismatches. The effectiveness of both methods has be verified by experiments.