Mixed Logic Style Decoders for Low Power High Speed Applications

Abstract

Power and delay are very important factors in the performance of any logic circuit. The emergence of various logics like modified GDI circuit, pass transistor logic and transmission gate logic have led to the development of various mixed logic circuits to improve performance. The fundamental difference between these logics is the providing of input signal to the gate and source terminals in the transistor. This work tries to come up with a mixed logic aiming for power and delay reduction which could be used for decoder design and the same have been compared in terms of metrics. The basic circuit of decoder has been simulated and analyzed using Cadence Virtuoso. Reduction of power and delay has been observed while using mixed logic design. The designed decoder circuit has been used as the base to design the full adder and significant performance improvement is noticed. The paper looks into the existing circuit used to realize the decoder and proposes a circuit using mixed logic style for achieving better performance.