E. Lind, M. Egard, Sofia Johansson, A. Johansson, B. Borg, C. Thelander, Karl‐Magnus Persson, A. Dey, L. Wernersson
{"title":"High frequency performance of vertical InAs nanowire MOSFET","authors":"E. Lind, M. Egard, Sofia Johansson, A. Johansson, B. Borg, C. Thelander, Karl‐Magnus Persson, A. Dey, L. Wernersson","doi":"10.1109/ICIPRM.2010.5516010","DOIUrl":null,"url":null,"abstract":"We report on RF characterization of vertical, 100-nm-gate length InAs nanowire MOSFETs, utilizing wrap-gate technology and Al<inf>2</inf>O<inf>3</inf> high-K gate oxide. The transistors show f<inf>t</inf>=5.6 GHz and f<inf>max</inf>=22 GHz, mainly limited by parasitic capacitances. The RF device performance is described using a hybrid-π model taking hole generation at the drain into account. Electrostatic modeling of the parasitic capacitances for arrays of vertical nanowires indicates that a strong reduction in extrinsic capacitances can be achieved for devices with a small inter-wire separation.","PeriodicalId":197102,"journal":{"name":"2010 22nd International Conference on Indium Phosphide and Related Materials (IPRM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 22nd International Conference on Indium Phosphide and Related Materials (IPRM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIPRM.2010.5516010","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
We report on RF characterization of vertical, 100-nm-gate length InAs nanowire MOSFETs, utilizing wrap-gate technology and Al2O3 high-K gate oxide. The transistors show ft=5.6 GHz and fmax=22 GHz, mainly limited by parasitic capacitances. The RF device performance is described using a hybrid-π model taking hole generation at the drain into account. Electrostatic modeling of the parasitic capacitances for arrays of vertical nanowires indicates that a strong reduction in extrinsic capacitances can be achieved for devices with a small inter-wire separation.