Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces

Abstract

Characteristics of the on-chip power supply noise in a 6.4 Gbps serial link interface test system are analyzed by both simulation and measurement techniques. Pre- and post-layout simulation methodologies are discussed with different on-chip power grid modeling approaches proposed and supply current profile extraction method established. An on-chip supply noise measurement technique is introduced to allow monitoring both the statistics and dynamics of supply noise. Good agreement between simulation results and measurement results from the test system transmitting PRBS7 data pattern at 6.4 Gbps are observed in time and frequency domain.