Security-aware VLSI design for speaker identification based on efficient SMO architecture

Abstract

Speaker identification is a popular investigation that is greatly applied in many applications such as human-machine interfaced, security systems, etc. In real life, low cost and fast response are both necessary features for speaker identification in stand-alone embedded device. However, most of the responding time occupies in training phase, and the cost of general solution by employing digital signal processors is too high. In this work, security-aware VLSI design with the efficient Sequential Minimal Optimization (SMO) architecture is proposed for solving the problems in text-independent speaker identification. Our contributions are attributed to the optimal VLSI design form algorithm to architecture level. At algorithm level, the proposed Improved SMO (ISMO) algorithm is adopted for efficient data selection and it can reduce 30% computation. At architecture level, a distributed and reconfigurable computing architecture which combines parallel and pipeline designing styles is implemented, and it provides the high flexible and high performance benefits. Finally, the experimental results show that the proposed design can save 50% of memory usage, and the hardware resources can be reduced by 31% than our previous work. Furthermore, the responding time can decrease 85%.