Charge-based on-chip measurement technique for the selective extraction of cross-coupling capacitances

Abstract

We present a simple test structure (derived from the CBCM technique proposed by Sylvester et al.) that enables the selective extraction of cross-coupling capacitance between arbitrary on-chip interconnects. We discuss the silicon implementation on a 0.18um CMOS process and report preliminary experimental results. The accurate characterization of wiring capacitance is a key task in the design and validation of deep sub micron (DSM) integrated circuits because of the growing impact of interconnects on performance, power and reliability. There are three main ways for characterizing wiring capacitances: i) parameter extraction from a 3D model derived from layout, ii) indirect measure by means of parametric model fitting, and iii)