{"title":"Capacitive Memory Using GLAD Synthesized Annealed SnO2 Nanowires Array as a Dielectric","authors":"Priyanka Chetri, J. C. Dhar","doi":"10.1109/VLSIDCS53788.2022.9811450","DOIUrl":null,"url":null,"abstract":"This paper presents the fabrication of as-deposited and annealed SnO<inf>2</inf> NWs via GLAD (glancing angle deposition) technique. On investigation, the 650 °C SnO<inf>2</inf> NWs show improvement in its crystallinity. The capacitive behavior of both the device was analyzed by evaluating the capacitance-voltage (CV) and conductance-voltage (G-V) characteristics for both asdeposited and annealed sample by varying frequencies. The annealed device showed improved capacitive memory with interface trap density (9.7×10<sup>9</sup> eV<sup>-1</sup>cm<sup>-2</sup>), charge storage density of 5.45×10<sup>10</sup> cm<sup>-2</sup> and memory window of ~ 0.89 V at ± 8V for 1MHz.","PeriodicalId":307414,"journal":{"name":"2022 IEEE VLSI Device Circuit and System (VLSI DCS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE VLSI Device Circuit and System (VLSI DCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIDCS53788.2022.9811450","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents the fabrication of as-deposited and annealed SnO2 NWs via GLAD (glancing angle deposition) technique. On investigation, the 650 °C SnO2 NWs show improvement in its crystallinity. The capacitive behavior of both the device was analyzed by evaluating the capacitance-voltage (CV) and conductance-voltage (G-V) characteristics for both asdeposited and annealed sample by varying frequencies. The annealed device showed improved capacitive memory with interface trap density (9.7×109 eV-1cm-2), charge storage density of 5.45×1010 cm-2 and memory window of ~ 0.89 V at ± 8V for 1MHz.
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