Measuring Integrated Electronic Device Geometry Via HF-NO-H 2 0 Vapor Stain

Abstract

The p-n junction geometry of active, passive, and integrated silicon devices is customarily determined by various liquid-stain and angle-lap methods. In fact, it has been necessary to develop many liquid-staining methods since the simultaneous evaluation of even simple combinations of p-n, n+n and p+p boundaries has not been possible within a single stain cycle. A novel vapor-staining method using nitrogen oxide (NO 2 or NO) and hydrogen fluoride overcomes shortcomings in such simultaneous boundary delineations. The simple vapor process performed in a fraction of a minute is directly and clearly observable with lowpower optics enabling exact control of the stain-pattern contrast to be obtained. Numerous epitaxial layer thicknesses and diffused junction depths have been measured easily via the vapor stain with an accuracy of better than 0.05 micron. The stain-process details and the results of measurements made on n-p-n and p-n-p transistor devices are presented.