Hybrid modified booth encoded algorithm-carry save adder fast multiplier

Abstract

One of the effective ways to speed up multiplication are by reducing the number of partial products and accelerating the accumulation. In this paper, a new architecture of hybrid Modified Booth Encoded Algorithm (MBE) and Carry Save Adder (CSA) is developed as fast multiplier architecture. Altera Quartus II platform is used to run the simulation. The architecture design is programmed into FPGA using Altera DE2 board to verify the synthesizability on physical hardware. This hybrid fast multiplier delivers good performance in term of higher speed as well as in term of less usage of logic elements.