Physical Assurance for Heterogeneous Integration: Challenges and Opportunities

Abstract

Integrated Circuit (IC) hardware assurance is an increasingly concerning topic for semiconductor industries. Because ICs are the industries’ fundamental building blocks, they are consistently targeted for adversarial attacks. Physical inspection methods (i.e., Scanning Electron Microscopy (SEM), X-ray, and THz) are used to verify the IC hardware from the transistor to the device level. However, these inspection methods are difficult to apply to emerging packaging technologies and Heterogeneous Integration (HI) due to their inherent limitations and sample complexity. HI complex nature can provide some inherent features employable as countermeasures. For instance, the material and the structural fingerprints can be used to monitor, verify, and provide device assurance. This paper will introduce potential security vulnerabilities in HI hardware and review various physical inspection methods and their limitations surrounding comprehensive assurance. Both non-destructive and destructive methods will be discussed, ranging from material/structural analysis to transistor-level physical inspection. Insights to the MEMS & NEMS implantation into the package to secure the original design, will be also explored in this paper.