FPGA implementation of network on chip framework using HDL

Abstract

Traditional System on Chip (SOC) designs offer integrated solutions to exigent design tribulations in areas which necessitate outsized computation and restriction in certain area. But the performance of these has been sluggish due to the restriction of the common bus architecture espoused by these systems and thereby low processing speeds. This has been the main stumbling block for scalability in terms of computation and enhancement in its performance. With the advancement in semi conductor devices and fabrication technology, it is possible to pack more logic in smaller area of silicon. But the implementation of these mega functional modules using common bus architecture, parallel bus architecture, pipelining are becoming ineffective and posing a bottleneck in terms of performance and throughput in this billion transistor era. As an elucidation for this problem, Network on chip is being adopted in this paper as the core bus architecture across different spectrum of SOCs. Our approach presents a supple design using FPGA based system. Hence, it is a very flexible network design that will accommodate to various needs.