A low-power 1.2 GHz 0.35 /spl mu/m CMOS PLL

Abstract

In this paper, a low-power high-speed CMOS PLL is presented. The PLL consists of a 1.2-GHz voltage controlled oscillator, a dead-zone free phase frequency detector, a charge pump, and a frequency divider. The circuit was fabricated using 0.35 /spl mu/m TSMC CMOS technology. The total power consumption is 9.6 mW at 1.2-GHz operating frequency with 1.5 V supply voltage. The phase noise is -94 dBc at 10 kHz offset.