Numerical Computation of Parasitic Slot Capacitances in Electrical Machines

Abstract

Parasitic capacitive couplings in the machine slots act as an undesired leakage current path. This paper presents a method to compute lumped capacitance values and their distribution through 2D electrostatic finite-element simulation. The method is applied to a real machine slot with double layer. Turn-to-iron and inter-turn capacitive couplings show that negligible values appear between distant turns and turns not facing the slot walls and the iron. This reduction of the matrix size can be exploited on further high-frequency equivalent circuit representation. In addition, the influence of the insulation geometry and characteristics is studied.