R. Póvoa, N. Lourenço, N. Horta, Rui Santos-Tavares, J. Goes
{"title":"A cascode-free single-stage amplifier using a fully-differential folded voltage-combiner","authors":"R. Póvoa, N. Lourenço, N. Horta, Rui Santos-Tavares, J. Goes","doi":"10.1109/ICECS.2014.7049972","DOIUrl":null,"url":null,"abstract":"This paper presents the design and the electrical simulations of a single-stage amplifier with high energy-efficiency and enhanced DC gain without the need of using any cascode devices or any positive-feedback or feed-forward techniques. Instead, a fully-differential folded voltage-combiner block is used in replacement of the traditional tail current-source that is normally employed to bias the differential-pair. Simulation results of the properly optimized circuit, using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that a DC gain above 50 dB can be achieved, together with high energy efficiency. A simulated figure-of-merit above 2200 MHz×pF/mA has been reached. The circuit was designed using a 130 nm CMOS technology, draining approximately 0.2 mA from a 1.2 V power supply.","PeriodicalId":133747,"journal":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2014.7049972","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
This paper presents the design and the electrical simulations of a single-stage amplifier with high energy-efficiency and enhanced DC gain without the need of using any cascode devices or any positive-feedback or feed-forward techniques. Instead, a fully-differential folded voltage-combiner block is used in replacement of the traditional tail current-source that is normally employed to bias the differential-pair. Simulation results of the properly optimized circuit, using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that a DC gain above 50 dB can be achieved, together with high energy efficiency. A simulated figure-of-merit above 2200 MHz×pF/mA has been reached. The circuit was designed using a 130 nm CMOS technology, draining approximately 0.2 mA from a 1.2 V power supply.