The study of sensitive circuit and layout for CDM improvement

Abstract

The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more important than the package capacitor for chip CDM since the well pick-up only can affect the current coming from bus line capacitors, but cannot affect the current coming from the package capacitor. Moreover, putting the circuit and ESD protection device in the deep-NWell to isolate the circuit from the P-substrate and using the long contact-to-contact space for ESD protection device also can get the better CDM performance.