FinFET based adiabatic logic design for low power applications

Abstract

The circuit behaviour in Adiabatic logic and FinFET Technology is studied in detail in the literature so as to improve the ultralow power design. The energy saved by adiabatic logic using FinFET is significant compared to the CMOS. This way of designing a circuit is effective in low speed operations where power consumption is more important than performance. Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS at the nanoscale. Finfet, a long channel device which improves electrostatic control over device. These low power requirements have emerged due to the advancement in technology where power is more important like medical, mobile phones, hand held devices etc. In subthreshold logic, the circuit operates with supply voltage less than that of the threshold voltage of the transistor and utilizes leakage current as the operating current. This is achieved as the dynamic power consumption is quadratic ally dependent on the supply voltage. To show the results we are implementing 4-bit adder in subthreshold adiabatic logic using FinFET technology which shows that the power consumed by FinFET adiabatic logic will be less than that of normal adiabatic operation operation. The analysis has been carried for 32nm FinFET models using HSPICE simulations. For performance analysis we also used industry standard Cadence® EDA tools.