N. Srivastava, G. Raghavan, R. Thiagarajah, M. Case, E. Arnold, C. Pobanz, S. Nielsen, J. Yen, R.A. Johnson
{"title":"InP HBT ring oscillator with 2.0 ps/stage gate delay","authors":"N. Srivastava, G. Raghavan, R. Thiagarajah, M. Case, E. Arnold, C. Pobanz, S. Nielsen, J. Yen, R.A. Johnson","doi":"10.1109/GAAS.2002.1049054","DOIUrl":null,"url":null,"abstract":"We have demonstrated a record gate delay of 2 ps/stage in a 17-stage ring oscillator fabricated in a 170 GHz f/sub t/, 150 GHz f/sub max/ InP HBT technology. Stable operation was achieved for both normal and higher order ring modes. We performed basic circuit time constant analysis as well as detailed computer simulations, and arrived at calculated gate delays which are in agreement with our experimental results. The approach of using stage delay from a ring oscillator as a technology speed metric can be misleading. Such an approach would predict 250 GHz circuits in this process - which is not feasible. Real circuits require fanout of two or more which can substantially increase gate delay. In our circuit, we focused on broad-banding each individual stage and reducing interconnect parasitics to achieve the above result.","PeriodicalId":142875,"journal":{"name":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.2002.1049054","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
We have demonstrated a record gate delay of 2 ps/stage in a 17-stage ring oscillator fabricated in a 170 GHz f/sub t/, 150 GHz f/sub max/ InP HBT technology. Stable operation was achieved for both normal and higher order ring modes. We performed basic circuit time constant analysis as well as detailed computer simulations, and arrived at calculated gate delays which are in agreement with our experimental results. The approach of using stage delay from a ring oscillator as a technology speed metric can be misleading. Such an approach would predict 250 GHz circuits in this process - which is not feasible. Real circuits require fanout of two or more which can substantially increase gate delay. In our circuit, we focused on broad-banding each individual stage and reducing interconnect parasitics to achieve the above result.