InP HBT ring oscillator with 2.0 ps/stage gate delay

N. Srivastava, G. Raghavan, R. Thiagarajah, M. Case, E. Arnold, C. Pobanz, S. Nielsen, J. Yen, R.A. Johnson
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引用次数: 4

Abstract

We have demonstrated a record gate delay of 2 ps/stage in a 17-stage ring oscillator fabricated in a 170 GHz f/sub t/, 150 GHz f/sub max/ InP HBT technology. Stable operation was achieved for both normal and higher order ring modes. We performed basic circuit time constant analysis as well as detailed computer simulations, and arrived at calculated gate delays which are in agreement with our experimental results. The approach of using stage delay from a ring oscillator as a technology speed metric can be misleading. Such an approach would predict 250 GHz circuits in this process - which is not feasible. Real circuits require fanout of two or more which can substantially increase gate delay. In our circuit, we focused on broad-banding each individual stage and reducing interconnect parasitics to achieve the above result.
具有2.0 ps/级门延迟的InP HBT环形振荡器
我们已经展示了在170 GHz f/sub /, 150 GHz f/sub max/ InP HBT技术中制造的17级环形振荡器中2 ps/级的创纪录门延迟。正常和高阶环模均能实现稳定运行。我们进行了基本的电路时间常数分析和详细的计算机模拟,得到了与实验结果一致的门延迟计算结果。使用环形振荡器的级延迟作为技术速度度量的方法可能会产生误导。这种方法将在这个过程中预测250千兆赫的电路——这是不可行的。实际电路需要两个或更多的扇出,这可以大大增加门延迟。在我们的电路中,我们专注于宽带每个阶段,并减少互连寄生,以实现上述结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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