FPGA - Based Compute Nodes for the PANDA Experiment at FAIR

W. Kuhn, C. Gilardi, D. Kirschner, J. Lang, S. Lange, Ming Liu, T. Perez, L. Schmitt, D. Jin, Lu Li, Zhen'An Liu, Yun-Ju Lu, Qiang Wang, Shujun Wei, Hao Xu, Dixin Zhao, K. Korcyl, J. Otwinowski, P. Salabura, I. Konorov, A. Mann
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引用次数: 17

Abstract

PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10**7 /s and data rates of several 100 Gb Is. FPGA based compute nodes with multi-Gbit/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Each board is equipped with 5 Virtex4 FX60 FPGAs. High bandwidth connectivity is provided by four Gbit Ethernet links and 8 additional optical links connected to RocketIO ports. A single ATCA crate can host up to 14 boards which are interconnected via a full mesh backplane.
基于FPGA的FAIR熊猫实验计算节点
PANDA是FAIR/GSI的HESR设施上的一种新的通用反质子物理探测器。PANDA数据采集系统必须处理10**7 /s数量级的交互速率和几个100gb的数据速率。基于FPGA的计算节点采用ATCA架构,具有多gbit /s带宽能力,用于处理事件构建、特征提取和高级触发处理等任务。每块板配有5个Virtex4 FX60 fpga。通过4 Gbit以太网链路和8个额外的光链路连接到RocketIO端口,提供高带宽连接。单个ATCA板条箱可容纳多达14块板,这些板通过全网格背板相互连接。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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