W. Kuhn, C. Gilardi, D. Kirschner, J. Lang, S. Lange, Ming Liu, T. Perez, L. Schmitt, D. Jin, Lu Li, Zhen'An Liu, Yun-Ju Lu, Qiang Wang, Shujun Wei, Hao Xu, Dixin Zhao, K. Korcyl, J. Otwinowski, P. Salabura, I. Konorov, A. Mann
{"title":"FPGA - Based Compute Nodes for the PANDA Experiment at FAIR","authors":"W. Kuhn, C. Gilardi, D. Kirschner, J. Lang, S. Lange, Ming Liu, T. Perez, L. Schmitt, D. Jin, Lu Li, Zhen'An Liu, Yun-Ju Lu, Qiang Wang, Shujun Wei, Hao Xu, Dixin Zhao, K. Korcyl, J. Otwinowski, P. Salabura, I. Konorov, A. Mann","doi":"10.1109/RTC.2007.4382729","DOIUrl":null,"url":null,"abstract":"PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10**7 /s and data rates of several 100 Gb Is. FPGA based compute nodes with multi-Gbit/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Each board is equipped with 5 Virtex4 FX60 FPGAs. High bandwidth connectivity is provided by four Gbit Ethernet links and 8 additional optical links connected to RocketIO ports. A single ATCA crate can host up to 14 boards which are interconnected via a full mesh backplane.","PeriodicalId":217483,"journal":{"name":"2007 15th IEEE-NPSS Real-Time Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 15th IEEE-NPSS Real-Time Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTC.2007.4382729","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17
Abstract
PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10**7 /s and data rates of several 100 Gb Is. FPGA based compute nodes with multi-Gbit/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Each board is equipped with 5 Virtex4 FX60 FPGAs. High bandwidth connectivity is provided by four Gbit Ethernet links and 8 additional optical links connected to RocketIO ports. A single ATCA crate can host up to 14 boards which are interconnected via a full mesh backplane.