Minimizing gate lag of a planar high-power GaAs MESFET by Al/sub 2/O/sub 3/ passivation and optimized gate process

Abstract

This study demonstrates that using ALD grown Al/sub 2/O/sub 3/ as a surface passivation layer, and by controlling the Al/sub 2/O/sub 3/ over-etch time, the gate lag of a planar high power GaAs MESFET can be controlled to an undetectable level. In addition, more than 30 V higher Vbkd was achieved when the Al/sub 2/O/sub 3/ surface passivation layer was employed. These results indicate that the above reported GaAs MESFET device is very promising for wireless base station high-power amplifier applications.