Performance analysis of vedic multiplication technique using FPGA

Abstract

Today, it is necessary to increase the speed of multiplier as the need of high speed processors is increasing. Multiplier is a main block of any processor. Conventional processors need great hardware resources and take more time in multiplication operation. This paper present a high speed multiplier based on ancient popular Vedic Mathematics. Implementation is done on digital circuits. Vedic multiplication is accomplished in the same way as that of normal multiplier using digital hardware. In this paper a comparison of concerned multipliers in 8, 16 and 32 bits multiplications is performed. 8 bit and 16bit Urdhva algorithm shows 50% improvement in delay than that of Nikhilam, whereas 100% better than that of Binary multiplier. 32bit Nikhilam multiplier gives 52% improvement in delay than that of Urdhva multiplier and 16% better than that of binary multiplier.