Area Efficient 4Gb/s Clock Data Recovery Using Improved Phase Interpolator with Error Monitor

Abstract

The paper presents area efficient 4Gbps clock and data recovery (CDR) by using improved phase interpolator (PI) with error monitor. The proposed CDR architecture has only two sets of phase interpolator while the conventional CDR has eight sets of phase interpolators. Each set of the PI is comprised of eight inverters to get 11.25°. phase interpolation from 0. to 348.75. by using the proposed phase error monitor. The outputs of the phase error monitor are composed of 9 bits sampled from early pulse. The monitor chooses four clock phases among 0., 45°, 90°, 135°, 180°, 225°, 270°, and 315° from an analog voltage controlled oscillator (VCO) by sending 3 bits to the mutiplexer. Then, the other 6 bits determine the interpolation phase of each block by using the inverter switches. Vcont (Charge Pump Output Voltage) is pre-charged to 345mV for fast locking time. The time for frequency locking and phase selection are 23.35ns with pre-charge time (1.1ns). The design is simulated with a 180nm CMOS technology node at 1.8V power supply. The total power consumption of the proposed CDR is 4.35mW.